reg[2:0] cstate,nstate;

　　reg[3:0] cnt;

　　always @(posedge clk or negedge rst_n)

　　if(!rst_n) cstate <= IDLE;

　　else cstate <= nstate;

　　always @(cstate or din or cnt) begin

　　case(cstate)

　　IDLE: begin

　　cnt = 4'd0;

　　if(din) nstate = STA1;

　　else nstate = IDLE;

　　end

　　STA1: begin

　　cnt = cnt+1'b1;

　　if(cnt == 4'd10) nstate = IDLE;

　　else nstate = STA1;

　　end

　　default: nstate = IDLE;

　　endcase

　　end

　　如果大家有興趣對三中代碼方式都做一下仿真，會發(fā)現(xiàn)一些有意思的問題，尤其兩段式狀態(tài)機最終根本無法退出STA1，計數(shù)器cnt也會死在那里。究其根本原因，可大有學(xué)問。在編譯工程后，出現(xiàn)了數(shù)條類似下面的warning：

　　Warning: Found combinational loop of 2 nodes

　　Warning: Node "Add0~2"

　　Warning: Node "cnt~9"

　　何為combinational loop?讓handbook來解釋吧，看不懂英文的可別怪我~_~

　　Combinational loops are among the most common causes of instability and unreliability in digital designs. They should be avoided whenever possible. In a synchronous design, feedback loops should include registers. Combinational loops generally violate synchronous design principles by establishing a direct feedback loop that contains no registers. For example, a combinational loop occurs when the left-hand side of an arithmetic expression also appears on the right-hand side in HDL code. A combinational loop also occurs when you feed back the output of a register to an asynchronous pin of the same register through combinational logic, as shown in Figure 5–1.

　　沒有寄存器打一拍的這種combinational loop(組合環(huán))是一種不推薦的設(shè)計方式，就如兩段式狀態(tài)機所實現(xiàn)的效果，甚至最終無法實現(xiàn)功能要求。同樣的功能，一段式和三段式狀態(tài)機之所以能夠解決這個問題，就是避免了在純組合邏輯中涉及這個反饋邏輯。在初學(xué)verilog時，我們常提的latch(鎖存器)，其實也是combinational loop的一個特例。