這個工程比較大，腳本運(yùn)行時(shí)間稍微會長一些時(shí)間，有興趣學(xué)習(xí)PCIE或者DMA的同學(xué)需要好好看PDF以及.v文件和仿真出來的波形，學(xué)習(xí)腳本的同學(xué)認(rèn)真看xilixn官網(wǎng)給出的腳本的寫法，你會受益匪淺。
3.常用腳本語言的解釋
#切換到工作目錄
cd F:/Projects/BeiJing/sim
vsim -novopt work.histogram_2d_new_tb

#結(jié)束仿真
quit -sim

#仿真video_cap模塊 不優(yōu)化
vsim -novopt work.video_cap_tb

##退出當(dāng)前仿真
quit -sim
##仿真image_src模塊 不優(yōu)化
vsim -novopt work.image_src

##設(shè)置仿真時(shí)間分辨率
##vsim -t 1ps? ?-lib work image_src
##設(shè)置仿真時(shí)間分辨率
vsim -t 1ns? ?-lib work AES256_tb?

##添加頂層所有的信號
add wave *

radix hex ##16進(jìn)制顯示
radix unsigned ##10進(jìn)制顯示

##編譯xilinx庫 VHDL?
vcom –work simprim d:Xilinx/VHDL/src/simprims/simprim_Vcomponents.vhd
vcom –work simprim d:Xilinx/VHDL/src/simprims/simprim_Vpackage.vhd
vcom –work simprim d:Xilinx/VHDL/src/simprims/simprim_VITAL.vhd
vcom –work unisim d:Xilinx/VHDL/src/unisims/unisim_VCOMP.vhd
vcom –work unisim d:Xilinx/VHDL/src/unisims/unisim_VPKG.vhd
vcom –work unisim d:Xilinx/VHDL/src/unisims/unisim_VITAL.vhd
vcom –work unisim d:Xilinx/VHDL/src/unisims/unisim_VCFG4K.vhd
vcom –work xilinxcorelib d:Xilinx/VHDL/src/ XilinxCoreLib/*.vhd

##編譯xilinx庫 Verilog
vlog –work simprim d:Xilinx/VHDL/src/simprims/simprim_Vcomponents.v
vlog –work simprim d:Xilinx/VHDL/src/simprims/simprim_Vpackage.v
vlog –work simprim d:Xilinx/VHDL/src/simprims/simprim_VITAL.v
vlog –work unisim d:Xilinx/VHDL/src/unisims/unisim_VCOMP.v
vlog –work unisim d:Xilinx/VHDL/src/unisims/unisim_VPKG.v
vlog –work unisim d:Xilinx/VHDL/src/unisims/unisim_VITAL.v
vlog –work unisim d:Xilinx/VHDL/src/unisims/unisim_VCFG4K.v
vlog –work xilinxcorelib d:Xilinx/VHDL/src/ XilinxCoreLib/*.v

#新建工程?

project new D:/work/test
project open test
project addfile test.vhd

project compileall

vsim -L lpm -L altera?

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