------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);

------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------

C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
LED => LED,
-- MAP USER PORTS ABOVE THIS LINE ------------------

Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);

------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;

user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);

end IMP;

137行
LED : out std_logic_vector(7 downto 0);

定義IP的端口為LED，這里需要和之前修改MPD文件一致。

232-268行為元件聲明
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 1;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
LED : out std_logic_vector(7 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------

-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;

323-352行為user_logic元件例化。VHDL是不區分大小寫的。
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------

C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
LED => LED,
-- MAP USER PORTS ABOVE THIS LINE ------------------

Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);

這幾個文件修改后保存。

Project->Rescan User Repositories（更新用戶倉庫？），讓XPS識別到對IP所做的修改

三、將自定義IP核添加到PS系統

同第三篇一樣，需要將IP添加到PS系統中。

在Ports標簽中，需要將我們定義的LED端口設置為外部端口，外部引腳名按照Zedboard的習慣，定義為LD

在Address標簽中，設定IP的地址。XPS支持自定義定制范圍、空間大小等。可以使用默認設置，也可以手動設置。這里我設置基地址為0x40000000，其實也就是我們設定的數據寄存器的地址為0x40000000。如果有更多的寄存器，會以4字節offset 地址的方式訪問即可。

最后一樣修改ucf文件，完成約束。
NET LD[0] LOC = T22 | IOSTANDARD=LVCMOS33; # "LD0"
NET LD[1] LOC = T21 | IOSTANDARD=LVCMOS33; # "LD1"
NET LD[2] LOC = U22 | IOSTANDARD=LVCMOS33; # "LD2"
NET LD[3] LOC = U21 | IOSTANDARD=LVCMOS33; # "LD3"
NET LD[4] LOC = V22 | IOSTANDARD=LVCMOS33; # "LD4"
NET LD[5] LOC = W22 | IOSTANDARD=LVCMOS33; # "LD5"
NET LD[6] LOC = U19 | IOSTANDARD=LVCMOS33; # "LD6"
NET LD[7] LOC = U14 | IOSTANDARD=LVCMOS33; # "LD7"

最后對這個系統編譯，生成bitstream文件，并將硬件配置導入到SDK，并啟動SDK。

四、使用SDK編寫IP核驅動程序和應用程序

打開SDK，可以從系統信息system.xml中看到我們的系統信息。可以看到我們實例化連接到系統的ip是my_axi_ip_0，基地址是0x4000000。

建立軟件工程后，修改main代碼，如下
//@超群天晴
#include
#include "xparameters.h"
#include "xil_types.h"
#include "xstatus.h"
#include "xil_io.h"http://包含xil_io頭文件，完成對絕對地址的訪問
#include "platform.h"

#define LED_DATA_REG 0x40000000

void print(char *ptr);
void delay(unsigned int delaytime);
void LED_Play(unsigned char led);

int main(void)
{

init_platform();

print("ZedBoard LAB4: MY_AXI_LEDs ");
print("超群天晴 2012年10月8日22:12:31 ");

LED_Play(0x03);
while(1);

cleanup_platform();

return 0;
}

void delay(unsigned int delaytime)
{
int i;
for(i=0;i7);
Xil_Out32(LED_DATA_REG,led);
delay(50000000);
}
}

定義了兩個函數
void delay(unsigned int delaytime);
void LED_Play(unsigned char led);

其中delay()為延時函數，參數為延時時間，100000000大約延時1s；

LED_Play()為LED流水燈函數，參數是流水初始值。在程序里面設定的是0x2，也就LD0、LD1最開始亮，然后流水。

其中第8行
#define LED_DATA_REG 0x40000000

使用宏定義，定義LED_DATA_REG，實際上就是自定義IP的基地址。

第44行
Xil_Out32(LED_DATA_REG,led);

使用了xil_io.h提供的絕對地址訪問函數Xil_Out32(u32 OutAddress, u32 Value)，定義如下
/*****************************************************************************/
/**
*
* Performs an output operation for a 32-bit memory location by writing the
* specified Value to the the specified address.
*
* @param OutAddress contains the address to perform the output operation
* at.
* @param Value contains the Value to be output at the specified address.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void Xil_Out32(u32 OutAddress, u32 Value)
{
/* write the contents of the I/O location and then synchronize the I/O
* such that the I/O operation completes before proceeding on
*/
*(volatile u32 *) OutAddress = Value;
SYNCHRONIZE_IO;
}