`timescale 1 ns/ 1 ns
module led1_vlg_tst();
reg eachvec;
reg clk;
reg rst;
reg cnt;                                              
wire led;
                        
led1 i1 ( 
 .clk(clk),
 .led(led),
 .rst(rst)
);
initial                                               
begin                                                 
                    
clk = 0;
rst = 0;
#100
rst = 1;                                          
end 
always #1 clk = ~clk;                                                 
endmodule

module led1(clk,rst,led);

input clk,rst;
output led;

parameter time_1 = 27'd5000_0000;

reg[26:0] cnt;
reg led;

always @(posedge clk or negedge rst)
   if(!rst)
    cnt <= 27'd0;
   else if(cnt == time_1)
    cnt <= 27'd0;
   else
    cnt <= cnt + 1'b1;
    
always @(posedge clk or negedge rst)
   if(!rst)
    led <= 1'b1;
   else if(cnt == time_1)
    led <= ~led;
   
endmodule
   

cnt 一直為x 怎么回事？？