1。我在ISE中啟動modelsim時出現了下面的錯誤
Loading work.tb_ic1_func
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.fifoctlr_ic_v2
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) fifoctlr_ic_v2.v(126): Instantiation of 'BUFGP' failed. The design unit was not found.
是什么原因？
“點到仿真模式，在source里面選中你建立工程選擇的芯片，然后看Processes，點開，有個compile HDL simulation library，運行一下就OK了”

2.ISE用modelsim仿真提示：# ** Error: (vish-4014) No objects found matching '*'.結果仿真時老是報錯：
# ** Error: (vish-4014) No objects found matching '*'.
# Error in macro ./test_top_tb.fdo line 10
# (vish-4014) No objects found matching '*'.
# while executing
# "add wave *"
解決辦法，改modelsim.ini文件中的一個參數：VoptFlow = 0

3.當對IP核修改后，用Modelsim仿真顯示：No entity is bound for inst 或 CE is not in the entity。（CE是改動后添加的一個管腳），從而仿真無結果。

解決辦法：首先選中該IP核的.xco文件點擊右鍵->屬性 將屬性改為 "Synthesis/Imp + Simulation."
然后將其對應的.v或.vhd文件的屬性也改為 "Synthesis/Imp + Simulation."

4.啟動modelsim后，沒有出錯，但是有warning：(vsim-3009) [TSCALE] - Module 'ODDR' does not have a `timescale directive in effect, but previous modules do.輸入信號均正確，調用的IP core或原語的輸出為高阻態。

解決辦法：modelsim中調用該IP core或原語的庫不匹配，在xilinx中找到其所在的庫unisims，并重新編譯至modelsim的UNISIMS_VER庫中。問題可得到解決。