The HMA510 is a high speed, low power CMOS 16 x 16-bit
parallel multiplier accumulator capable of operating at 45ns
clocked multiply-accumulate cycles. The 16-bit X and Y
operands may be specified as either two’s complement or
unsigned magnitude format. Additional inputs are provided
for the accumulator functions which include: loading the
accumulator with the current product, adding or subtracting
the accumulator contents and the current product, and preloading
the Accumulator Registers from the external inputs.
All inputs and outputs are registered. The registers are all
positive edge triggered, and are latched on the rising edge of
the associated clock signal. The 35-bit Accumulator Output
Register is broken into three parts. The 16-bit least significant
product (LSP), the 16-bit most significant product
(MSP), and the 3-bit extended product (XTP) Registers. The
XTP and MSP Registers have dedicated output ports, while
the LSP Register shares the Y-inputs in a multiplexed fashion.
The entire 35-bit Accumulator Output Register may be
preloaded at any time through the use of the bidirectional
output ports and the preloaded control.