1CDC常見錯(cuò)誤

1.1Reconvergence

1.1.1single_source_reconvergence

結(jié)構(gòu)：同一個(gè)信號(hào)源頭，兩個(gè)同步處理器。這里提一下，有兩個(gè)CDC分析工具的參數(shù)配置：

1.1.2案列1：divergence_depths為0

// divergence point
always @ (posedge tx_clk)
    ctrl <= ci0 | ci1 ;
 
// two_dff synchronizer
always @ (posedge rx_clk) begin: two_dff
    reg temp;
    temp <= ctrl;
    two_dff_sync <= temp;
end
 
// shift_reg synchronizer
always @ (posedge rx_clk) begin: shift_reg
    shift_reg_sync <= {shift_reg_sync[0], ctrl};
end
 
// reconvergence point
always @ (posedge rx_clk)
    dout <= two_dff_sync ^ shift_reg_sync[1];
 

電路如下：divergence_depth為0

CDC報(bào)告如下：

1.2Redundant

案例1：

// two_dff synchronizer of tx_sig
always @ (posedge rx_clk) begin: two_dff
    reg s0 , s1;
    s0 <= tx_sig; // 1st flop
    s1 <= s0; // 2nd flop
end


// two_dff synchronizer of tx_sig
always @ (posedge rx_clk) begin: shift_reg
    reg [1:0] sh_reg;
    sh_reg?<=?{sh_reg[0],?tx_sig};
end

1.3multi_sync_mux_select (DMUX)

MUX的sel端fan-in信號(hào)超過一組同步器，不推薦。通常MUX的sel端只能有一組同步器。

案例1：

always @(posedge rx_clk) begin
    reg s1_sel1, s2_sel1;
    reg [1:0] s_sel2;
    
    s1_sel1 <= tx_sel1;
    s2_sel1 <= s1_sel1;
    
    s_sel2 <= {s_sel2[0], tx_sel2};
    
    if (s_sel2[1] | s2_sel1)
????????rx_data?<=?tx_data;
end

電路如下：

1.4combo_logic

1.4.1錯(cuò)誤案列1

always @ (posedge rx_clk) begin
    s1 <= tx_sig & din;
    s2 <= s1;
end

當(dāng)然還有如下這種錯(cuò)誤，除非additional logic全部是靜態(tài)變量。

1.5async_reset_no_sync（異步復(fù)位、同步撤離）

1.5.1案列1

// Reset triggered by tx_clk
always @(posedge tx_clk)
tx_sig <= rst;
 
// Unsynchronized reset used in
// Rx domain
always @(posedge rx_clk,negedge tx_sig)
if?(!tx_sig)?rx_sig?<=?1’b0;
else rx_sig <= din;

1.5.2錯(cuò)誤案列2

// Reset triggered by tx_clk
always @(posedge tx_clk)
tx_sig <= rst;
// Improperly synchronized reset used
// in Rx domain
always @(posedge rx_clk,negedge tx_sig)
if (!tx_sig) rx_reset <= 1’b0;
else rx_reset <= 1’b1;

正確的結(jié)構(gòu)如下：

1.6dff_sync_gated_clk

案列1，與門做時(shí)鐘gating有毛刺，需要clock gating cell。

// gated clock expression
assign gclk = rx_clk & clk_en;
always @(posedge gclk)
    sync1 <= tx_sig; // 1st DFF
always @(posedge rx_clk)
    sync2 <= sync1; // 2nd DFF

1.7fanin_different_clks

同步器的輸入由兩個(gè)異步時(shí)鐘域的組合邏輯構(gòu)成，如下圖所示：（還有combo logic）

值得注意的是，如果sig_a或者sig_b中有一個(gè)信號(hào)是stable靜態(tài)變量，那么上圖結(jié)構(gòu)的電路就不會(huì)被報(bào)fanin_different_clks或者combo_logic錯(cuò)誤。

假設(shè)有sig_a、sig_b、sig_c三個(gè)信號(hào)及以上的fan_in呢？拋開靜態(tài)變量后，

若所有信號(hào)都是同一個(gè)時(shí)鐘域，CDC錯(cuò)誤類型就是combo_logic；

若所有信號(hào)來自至少2個(gè)時(shí)鐘域，CDC錯(cuò)誤類型就是fanin_different_clks；

舉個(gè)例子，如下圖：

上圖電路仍會(huì)報(bào)fanin_different_clks，但是電路確實(shí)是設(shè)計(jì)者的意圖，我們只需要將TEST時(shí)鐘域的test_sel設(shè)置為常數(shù)0即可。

1.7.1案列1

always @ (posedge tx1_clk)
    tx1_sig <= in1;
always @ (posedge tx2_clk)
    tx2_sig <= in2;
always @ (posedge rx_clk) begin
    sync0 <= tx1_sig | tx2_sig;
    sync1 <= sync0;
end

審核編輯：劉清