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作為SpinalHDL語法篇的第一節，我們也從最簡單的開始。

Bool類型定義

Bool類型就是Verilog中的單bit類型，定義方式如下：

Syntax	Description	Return
Bool()	創建Bool類型變量	Bool
True	創建Bool類型變量，并賦值true	Bool
False	創建Bool類型變量，并賦值false	Bool
Bool(value: Boolean)	創建Bool類型變量，并使用Scala表達式賦值	Bool

Example：

vala=Bool()
valb=True
valc=False
vald=Bool(1>2)

生成的Verilog代碼如下：

wirea;
wireb;
wirec;
wired;

assignb=1'b1;
assignc=1'b0;
assignd=1'b0;

邏輯運算

下圖為官方的邏輯運算解釋，也不翻譯了，很容易理解。

Operator	Description	Return type
!x	Logical NOT	Bool
x && y	Logical And	Bool
x & y	Logical And	Bool
x \|\| y	Logical OR	Bool
x \| y	Logical OR	Bool
x ^ y	Logical XOR	Bool
x.set[()]	Set x to True	Bool
x.clear[()]	Set x to False	Bool
x.setWhen(cond)	Set x when cond is True	Bool
x.clearWhen(cond)	Clear x when cond is True	Bool
x.riseWhen(cond)	Set x when x is False and cond is True	Bool
x.fallWhen(cond)	Clear x when x is True and cond is True	Bool

vale=a&b
valf=a|b
valg=a^b
valh=!a

vali=Bool()
i.set()
valj=Bool()
j.clear()

valk=True#這里必須有初值，否則下一句會報錯
k.clearWhen(b)

vall=True
when(b){
l:=False
}

valm=RegInit(False)#關于寄存器類型，這里先熟悉一下，后面章節會講到
m.riseWhen(b)

邊緣檢測

Operator	Description	Return type
x.edge[()]	Return True when x changes state	Bool
x.edge(initAt: bool)	Same as x.edge but with a reset value	Bool
x.rise[()]	Return True when x was low at the last cycle and is now high	Bool
x.rise(initAt: Bool)	Same as x.rise but with a reset value	Bool
x.fall[()]	Return True when x was high at the last cycle and is now low	Bool
x.fall(initAt: Bool)	Same as x.fall but with a reset value	Bool
x.edges[()]	Return a bundle (rise, fall, toggle)	BoolEdges
x.edges(initAt: Bool)	Same as x.edges but with a reset value	BoolEdges

vala=Bool()
valb=False
when(a.edge()){
b:=True
}
valc=a.edge(False)

轉換后的代碼為：

moduleDemoBool(
inputclk,
inputreset
);

wirea;
regb;
rega_regNext;
wirewhen_DemoBool_l35;
rega_regNext_1;
wirec;

always@(*)begin
b=1'b0;
if(when_DemoBool_l35)begin
b=1'b1;
end
end

assignwhen_DemoBool_l35=(a^a_regNext);
assignc=(a^a_regNext_1);
always@(posedgeclk)begin
a_regNext<=?a;
??end

??always?@(posedge?clk?or?posedge?reset)?begin
????if(reset)?begin
??????a_regNext_1?<=?1'b0;
????end?else?begin
??????a_regNext_1?<=?a;
????end
??end

endmodule

valedgeBundle=myBool_2.edges(False)
when(edgeBundle.rise){
//dosomethingwhenarisingedgeisdetected
}
when(edgeBundle.fall){
//dosomethingwhenafallingedgeisdetected
}
when(edgeBundle.toggle){
//dosomethingateachedge
}

數值比對