資料介紹
The GGL301 is a single-chip implementation of a HomePlug? AV transceiver for inhome
networking over existing powerlines. By fully integrating all of the functions into a
single 100-lead TQFP package, the GGL301 provides the most compact and cost
effective solution for HomePlug? AV adapters and embedded applications.
Xtendnet? technology is used to increase total coverage and throughput in larger
networks. Xtendnet? enables each device to work as a repeater. So that each node
added to a network will regenerate and re amplify the signals over the powerlines.
The device consists of a fully integrated analog front-end, DSP based digital front-end,
HomePlug? AV Media Access Controller, RAM for buffer memory and control, an
advanced packet switching engine, and IEEE 802.3 Media Access Controller. The onchip
analog front-end includes a line driver that meets global requirements for injected
power and emissions, with bypass for applications needed an external line driver.
The device operates from a single 32MHz crystal, and can generate the 25MHz clock
commonly needed for Ethernet PHY devices.
networking over existing powerlines. By fully integrating all of the functions into a
single 100-lead TQFP package, the GGL301 provides the most compact and cost
effective solution for HomePlug? AV adapters and embedded applications.
Xtendnet? technology is used to increase total coverage and throughput in larger
networks. Xtendnet? enables each device to work as a repeater. So that each node
added to a network will regenerate and re amplify the signals over the powerlines.
The device consists of a fully integrated analog front-end, DSP based digital front-end,
HomePlug? AV Media Access Controller, RAM for buffer memory and control, an
advanced packet switching engine, and IEEE 802.3 Media Access Controller. The onchip
analog front-end includes a line driver that meets global requirements for injected
power and emissions, with bypass for applications needed an external line driver.
The device operates from a single 32MHz crystal, and can generate the 25MHz clock
commonly needed for Ethernet PHY devices.
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