ABSTRACT
Frequency synthesizers are used in a large number of time
division multiplexed (TDMA) and frequency hopping wireless
applications where quickly attaining frequency lock is
critical. A new frequency synthesizer is described which employs
a scheme for reducing lock time by a factor of two
using a conventional phase locked loop architecture. Faster
lock is attained by shifting the loop filter's zero and pole
corner frequencies while maintaining the PLL's gain/phase
margin characteristics.
INTRODUCTION
RF system designers of TDMA based cellular systems, such
as PHS, GSM and IS-54, need local oscillator (L.O.) or frequency
synthesizer blocks capable of tuning to a new channel
within a small fraction of each time slot. The suppression
of reference spurs and phase noise is also critical for
these modern digital standards. Base station and data
transmission applications are now striving to utilize all the
time slots available in each frame using a single synthesizer.
This push towards a ``zero blind slot'' solution has put stringent
demands upon the radio frontend's L.O. section.
The communication systems channel spacing determines
the upper bound for the synthesizer's frequency resolution
and loop filter bandwidth. More closely spaced channels
dictate that the synthesizer's frequency resolution be finer,
which in turn means the loop makes frequency corrections
less often. A wider loop filter bandwidth would make it easier
to attain lock within a given time constraint, but the price
paid is less attenuation of the reference frequency sidebands
and a higher integrated phase noise for the locked
condition. An examination of the equations which govern
the responsiveness of a closed loop system will provide
some solutions to this dilemma.