This 14-bit registered buffer is designed for 2.3-V to 2.7-V V_CC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications.

The SN74SSTVF16857 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. In addition, when RESET\ is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.