GENERAL DESCRIPTION
The DS28E01-100 combines 1024 bits of EEPROM
with challenge-and-response authentication security
implemented with the ISO/IEC 10118-3 Secure Hash
Algorithm (SHA-1). The 1024-bit EEPROM array is
configured as four pages of 256 bits with a 64-bit
scratchpad to perform write operations. All memory
pages can be write protected, and one page can be
put in EPROM-emulation mode, where bits can only
be changed from a 1 to a 0 state. Each DS28E01-
100 has its own guaranteed unique 64-bit ROM
registration number that is factory lasered into the
chip. The DS28E01-100 communicates over the
single-contact 1-Wire? bus. The communication
follows the standard Dallas Semiconductor 1-Wire
protocol with the registration number acting as node
address in the case of a multidevice 1-Wire network.
APPLICATIONS
Printer Cartridge Configuration and Monitoring
Medical Sensor Authentication and Calibration
System Intellectual Property Protection
TYPICAL OPERATING CIRCUIT