Interface Circuits for TIA/EIA-644 (LVDS)
ABSTRACT
This design note provides information concerning the designing of TIA/EIA-644 interface
circuits. The TIA/EIA-644 standard is discussed including electrical characteristics,
interconnections, line termination, and noise immunity. Finally, eye patterns are used to
measure the effects of signal distortion, noise, signal attenuation, and the resultant
intersymbol interference (ISI) in a data transmission system.
General Information
TIA/EIA-644, otherwise known as LVDS, is a signaling method used for
high-speed, low-power transmission of binary data over copper. This signaling
technique uses lower output-voltage levels than the 5-V differential standards
(such as TIA/EIA-422) to reduce power consumption, increase switching speed,
and allow operation with a 3.3-V supply rail. The LVDS current-mode drivers
create a differential voltage (247 mV to 454 mV) across a 100-Ω load. The LVDS
receivers detect signals as low as ±100 mV with as much as ±1-V ground noise.
TI offers LVDS receivers capable of recovering data over a common mode range
from –4 V to 5 V, which allows up to 3 V of ground noise. These receivers are
designated SN65LVDS33 and SN65LVDS34. The standard specifies a
theoretical maximum of 1.923 Gbit/s.
The intended application of this signaling technique is for baseband data
transmission over controlled impedance media of approximately 100 Ω, where
the transmission media may be printed-circuit board (PCB) traces, backplanes,
or cables. The ultimate rate and distance of data transfer is dependent upon the
attenuation characteristics of the media and the noise coupling from the
environment.
Figure 1 shows a typical connection with LVDS drivers and receivers. The data
inputs to the quad driver are received at the interface of the PCB traces from the
host controller. The data inputs consist of up to n+1 bits of information and a
transmit (Tx) clock. The data and clock signals are then transmitted differentially
to the interface of the quad driver outputs, to the interconnecting traces, and to
the host PCB connector. The signals then propagate from the interface of the host
PCB connector to the cable connector to the balanced interconnecting media. At
the plug on the other end of the cable, the signals pass through the cable plug,
the target connector interface, and then to the target PCB traces. The LVDS
signal path ends at the interface of the target PCB traces and the termination
circuit. An additional interface is located at the points where the PCB traces to the
quad receiver inputs are connected. The outputs of the receiver interface to the
target PCB traces and then on to the receiving controller.