Fundamental VCO frequency range: 10 GHz to 20 GHz VCO phase noise improvement of up to 3 dB as compared to ADF4382? Integrated RMS jitter at 20 GHz = 18 fs (integration bandwidth: 100 Hz to 100 MHz) Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method) VCO fast calibration time: <2 μs VCO autocalibration time: <100 μs Phase noise floor: ?156 dBc/Hz at 20 GHz PLL specifications ?239 dBc/Hz: normalized in-band phase noise floor (integer mode) ?287 dBc/Hz: normalized 1/f phase noise floor 625 MHz maximum phase/frequency detector input frequency 4.5 GHz reference input frequency Typical spurious fPFD: ?90 dBc Reference to output delay specifications Propagation delay temperature coefficient: 0.06 ps/°C Adjustment step size: <1 ps Multichip output phase alignment 3.3 V and 5 V power supplies ADIsimPLL? loop filter design tool support 7 mm × 7 mm, 48-terminal LGA ?40°C to +105°C operating temperature The ADF4383 is a high performance, ultra-low jitter, fractional-Nphased-locked loop (PLL) with an integrated voltage controlledoscillator (VCO) ideally suited for local oscillator (LO) generationfor 5G applications or data converter clock applications. The highperformance PLL has a figure of merit of ?239 dBc/Hz, low 1/fnoise and high PFD frequency of 625 MHz in integer mode that canachieve ultra-low in-band noise and integrated jitter. The ADF4383can generate frequencies in a fundamental octave range of 10 GHzto 20 GHz, thereby eliminating the need for subharmonic filters. Theoutput dividers on the ADF4383 allows a complete output frequencyrange to be generated from 625 MHz to 20 GHz.For multiple data converter clock applications, the ADF4383 automaticallyaligns its output to the input reference edge by includingthe output divider in the PLL feedback loop. For applicationsthat require deterministic delay or delay adjustment capability, aprogrammable reference to output delay with <1 ps resolution isprovided. The reference to output delay matching across multipledevices and over temperature allows predictable and precise multichipalignment.The simplicity of the ADF4383 block diagram eases developmenttime with a simplified serial peripheral interface (SPI) register map,external SYNC input, and repeatable multichip alignment in bothinteger and fractional mode.APPLICATIONSHigh performance data converter clocking Wireless infrastructure (MC-GSM, 5G, 6G) Test and measurement