The CY62157E is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life? （MoBL?） in portable applications. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Place the device into standby mode when deselected （CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH）。 The input or output pins （I/O0 through I/O15） are placed in a high impedance state when： ■ Deselected （CE1HIGH or CE2 LOW） ■ Outputs are disabled （OE HIGH） ■ Both Byte High Enable and Byte Low Enable are disabled （BHE， BLE HIGH） ■ Write operation is active （CE1 LOW， CE2 HIGH and WE LOW） To write to the device， take Chip Enable （CE1 LOW and CE2 HIGH） and Write Enable （WE） inputs LOW. If Byte Low Enable （BLE） is LOW， then data from I/O pins （I/O0 through I/O7）， is written into the location specified on the address pins （A0 through A18）。 If Byte High Enable （BHE） is LOW， then data from I/O pins （I/O8 through I/O15） is written into the location specified on the address pins （A0 through A18）。 To read from the device， take Chip Enable （CE1 LOW and CE2 HIGH） and Output Enable （OE） LOW while forcing the Write Enable （WE） HIGH. If Byte Low Enable （BLE） is LOW， then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable （BHE） is LOW， then data from memory appears on I/O8 to I/O15. See Truth Table on page 12 for a complete description of read and write modes. The CY62157E device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. For a complete list of related documentation， click here.