These TTL circuits feature dual 1-line-to-4-line demultiplexers
with individual strobes and common binary-address inputs
in a single 16-pin package. When both sections are
enabled by the strobes, the common address inputs sequentially
select and route associated input data to the appropriate
output of each section. The individual strobes permit
activating or inhibiting each of the 4-bit sections as desired.
Data applied to input C1 is inverted at its outputs and
data applied at C2 is true through its outputs. The inverter
following the C1 data input permits use as a 3-to-8-line decoder,
or 1-to-8-line demultiplexer, without external gating.Input clamping diodes are provided on these circuits to minimize
transmission-line effects and simplify system design.

Features
Y Applications:
Dual 2-to-4-line decoder
Dual 1-to-4-line demultiplexer
3-to-8-line decoder
1-to-8-line demultiplexer
Y Individual strobes simplify cascading for decoding or
demultiplexing larger words
Y Input clamping diodes simplify system design