The Cypress S34ML01G1， S34ML02G1， and S34ML04G1 series is offered with a 3.3-V VCC power supply， and with ×8 or ×16 I/O interface. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for ×8 is （2048 + 64 spare） bytes; for ×16 （1024 + 32） words. Each block can be programmed and erased up to 100，000 cycles with ECC （error correction code） on. To extend the lifetime of NAND flash devices， the implementation of an ECC is mandatory. The chip supports CE# don‘t care function. This function allows the direct download of the code from the NAND flash memory device by a microcontroller， since the CE# transitions do not stop the read operation. The devices have a Read Cache feature that improves the read throughput for large files. During cache reading， the devices load the data in a cache register while the previous data is transferred to the I/O buffers to be read. Like all other 2-kB page NAND flash devices， a program operation typically writes 2112 bytes （×8）， or 1056 words （×16） in 200 μs and an erase operation can typically be performed in 2 ms （S34ML01G1） on a 128-kB block （×8） or 64-kword block （×16）。 In addition， thanks to multiplane architecture， it is possible to program two pages at a time （one per plane） or to erase two blocks at a time （again， one per plane）。 The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by 50%. In multiplane operations， data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as the ports for command and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different densities， without any rearrangement of the footprint.