Abstract — Good understanding of power loss in a high frequency
synchronous buck converter is important for design optimization
of both power MOSFET and circuit itself. Most of the MOSFET
power losses are relatively easy to quantify. The exception is the
power loss associated with Cdv/dt induced turn on of the low-side
MOSFET (synchronous rectifier). This paper characterizes the
Cdv/dt induced power loss in two ways. First, detailed device
characterization, in-circuit testing, and modeling are used for a
comparative loss calculation. This method requires specialized
test equipment and is rather complicated and time consuming. A
simple method is then introduced to very accurately quantify the
Cdv/dt loss. With this method, the impacts of the Cdv/dt power
loss on synchronous buck converters at different operation
conditions can be readily assessed. The impacts of Cdv/dt
induced turn on different applications are addressed.