This example shows how to update at regulate period the WWDG counter using the
Early Wakeup interrupt (EWI).

The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI is
enabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDG
ISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07
is toggled.
The EXTI line9 is connected to PB.09 pin and configured to generate an interrupt
on falling edge.
In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0
and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT).

The EXTI Line9 will be used to simulate a software failure: once the EXTI line9
event occurs (by pressing Key push-button on EVAL board) the correspondent interrupt
is served, in the ISR the led connected to PC.07 is turned off and the EXTI line9
pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR and
the WWDG ISR will never be entered(WWDG counter not updated). As result, when the
WWDG counter falls to 3Fh the WWDG reset occurs.
If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed in
the WWDG ISR which prevent from WWDG reset.

If the WWDG reset is generated, after resuming from reset a led connected to PC.06
is turned on.

In this example the system is clocked by the HSE(8MHz).