ZBT SRAM Controller Reference Design for APEX II Devices

As communication systems require more low-latency, high-bandwidth
interfaces for peripheral components, designs need high-throughput
memory with efficient bus utilization. The previous generation of static
memory types are inefficient when they frequently switch between
reading from and writing to the memory. To address this problem, IDT,
Micron, and Motorola have developed the new zero-bus turnaround
(ZBT) SRAM architecture. To implement this new memory, Altera has
developed a ZBT SRAM controller reference design for use with
APEXTM II devices.
This application note describes the functionality of the Altera? ZBT
SRAM controller reference design and explains the data tree structure,
along with installation, compilation, and simulation, of the design file.