This project contains two folders:
?sim - Simulation models for the project
?syn - Synthesis models for the project

A Xilinx ISE 9.2i project has been setup in the syn directory, which
already contains both the simulation and synthesis files that have been
provided.

You are required to complete the decoder.vhd according to the memory
map guidelines given out during lectures. Once the decoder is
syntactically correct, you can run a simulation in questa using the
testbench provided.

The simulation testbench provides basic checks to ensure correct
read/write operations to memory and IO devices and should run to
completion given a fully operational decoder implementation.

Once the decoder is complete, you should add a ucf file to the project
and synthesise it to create a jedec file suitable for download to the
CPLD on the project boards.