2. General Description 3
3. Block Diagram4
4. Pin Assignments 5
5. Pin Descriptions.7
5.1 Media Connection Pins ..7
5.2 Configuration Pins 7
5.3 Port4 External MAC Interface Pins..8
5.4 Miscellaneous Pins.13
5.5 Per Port LED Pins ..14
5.6 Power Pins..15
5.7 Reserved Pins 16
5.8 Serial EEPROM and SMI Pins.16
5.9 Strapping Pins ..17
5.10 Port Status Strapping Pins 19
6. Register Description.21
6.1 PHY0 to 4: PHY Register of Each Port22
6.1.1 Register0: Control Register .22
6.1.2 Register1: Status Register.23
6.1.3 Register4: Auto-Negotiation Advertisement Register..23
6.1.4 Register5: Auto-Negotiation Link Partner Ability Register..24
6.1.5 Register6: Auto-Negotiation Expansion Register.24
6.2 PHY0: EEPROM Register0 ..25
6.2.1 Register16: EEPROM Byte0 and 1 Register ..25
6.2.2 Register17: EEPROM Byte2 and 3 Register ..25
6.2.3 Register18~20: EEPROM EthernetID Register.25
6.2.4 Register21: EEPROM Byte10 and 11 Register .26
6.2.5 Register22: EEPROM Byte12 and 13 Register .26
6.3 PHY1: EEPROM Register1 ..27
6.3.1 Register16~23: EEPROM (Byte 14~29) Register27
6.3.2 Register24~31: EEPROM VLAN (Byte 30~44) Register.27
6.4 PHY2: Pin & EEPROM Register28
6.4.1 Register16: Pin Register 28
6.4.2 Register17: Pin & EEPROM Register for VLAN29
6.5 PHY3: Port Control Register.30
6.5.1 Register16: Port Control Register.30
6.5.2 Register17: EEPROM (Byte 46) Register 31
6.5.3 Register18~20: EEPROM (Byte 47~52) Register31
7. Functional Description ..32
7.1 Switch Core Functional Overview .32
7.1.1 Application ..32
7.1.2 Port4 32
7.1.3 Port Status Configuration .36
7.1.4 Enable Port ..36
7.1.5 Flow Control37
7.1.6 Address Search, Learning and Aging .38
7.1.7 Address Direct Mapping Mode..38
7.1.8 Half Duplex Operation ..38
7.1.9 Inter-Frame Gap 38
7.1.10 Illegal Frame.38
7.2 Physical Layer Functional Overview .. 39
7.2.1 Auto-Negotiation for UTP.. 39
7.2.2 10Base-T Transmit Function . 39
7.2.3 10Base-T Receive Function 39
7.2.4 Link Monitor.. 39
7.2.5 100Base-TX Transmit Function 39
7.2.6 100Base-TX Receive Function . 39
7.2.7 100Base-FX 39
7.2.8 100Base-FX Transmit Function 40
7.2.9 100Base-FX Receive Function . 40
7.2.10 100Base-FX Far-End-Fault-Indication (FEFI) 40
7.2.11 Reduced Fiber Interface . 40
7.2.12 Power Saving Mode. 40
7.2.13 Reg0.11 Power Down Mode 40
7.2.14 Crossover Detection and Auto Correction? 41
7.2.15 Polarity Detection and Correction. 41
7.3 Advanced Functional Overview. 42
7.3.1 Reset .. 42
7.3.2 Setup and Configuration .. 42
7.3.3 Example of Serial EEPROM: 24LC02 . 43
7.3.4 24LC02 Device Operation .. 43
7.3.5 SMI . 44
7.3.6 Head-Of-Line Blocking? 44
7.3.7 802.1Q Port Based VLAN.. 44
7.3.8 QoS Function . 46
7.3.9 Insert/Remove VLAN Priority Tag. 46
7.3.10 Filtering/Forwarding Reserved Control Frame47
7.3.11 Broadcast Storm Control 47
7.3.12 Broadcast In/Out Drop 47
7.3.13 Loop Detection .. 48
7.3.14 MAC Loopback return to External .. 49
7.3.15 Reg0.14 PHY Loopback return to Internal .. 50
7.3.16 LED . 50
7.3.17 2.5V Power Generation.. 52
7.3.18 Crystal/Oscillator .. 52
8. Serial EEPROM Description. 53
9. Electrical Characteristics? 57
9.1 Absolute Maximum Ratings: 57
9.2 Operating Range: 57
9.3 DC Characteristics. 57
9.4 AC Characteristics. 58
9.5 Digital Timing Characteristics. 59
9.6 Thermal Data 59
10. Application Information? 60
10.1 UTP (10Base-T/100Base-TX) Application? 60
10.2 100Base-FX Application: 62
11. System Application Diagram.. 63
12. Design and Layout Guide . 64
13. Mechanical Dimensions . 65