The thickness of gate oxide in advanced CMOS technologies has

　　been scaled down to improve circuit operating speed. However，

　　the I/O circuits must drive or receive high-voltage signals to communicate with other ICs in the microelectronic system. To solve

　　the gate-oxide reliability issue without using additional thick

　　gate oxide process ［1］， the stacked-NMOS configuration has been

　　widely used in mixed-voltage I/O interfaces ［1］， ［2］。 But， stackedNMOS often have much lower electrostatic discharge （ESD） level

　　and slower turn-on speed， as compared with single NMOS ［3］。 In

　　this work， a novel ESD protection design with a high-voltage-tolerant power-rail ESD clamp circuit is designed to protect the

　　mixed-voltage I/O interfaces against ESD stresses in a 0.13μm

　　1.2V CMOS process.