On-chip modules available within the family include the following features： ? Two identical dual issue， 32-bit CPU core complexes （e200z7）， each with – Power Architecture embedded specification compliance – Instruction set enhancement allowing variable length encoding （VLE）， optional encoding of mixed 16-bit and 32-bit instructions， for code size footprint reduction – Signal processing extension （SPE） instruction support for digital signal processing （DSP） – Single-precision floating point operations （FPU） – 16 KB I-Cache and 16 KB D-Cache – Hardware cache coherency between cores ? 16 Hardware semaphores ? 3 channel CRC module ? 6MB on-chip flash – Supports read during program and erase operations， and multiple blocks allowing EEPROM emulation ? 384KB on-chip general-purpose SRAM including 48KB of standby RAM ? Two multi-channel direct memory access controllers （eDMA） – 64 channels per eDMA ? Dual core Interrupt controller （INTC） ? Phase-locked loop with FM modulation （FMPLL） ? Crossbar switch architecture for concurrent access to peripherals， flash， or RAM from multiple bus masters ? External Bus Interface （EBI） for calibration and application development ? System integration unit （SIU） with error correction status module （ECSM） ? Four protected port output pins （PPO） ? Boot assist module （BAM） supports serial bootload via CAN or SCI ? Three second-generation enhanced time processor units （eTPU2