I. Instructions for Interrupt Operation： 1. If “IE” instruction （interrupt enable） is set outside the interrupt processing program and there is “HALT” or “STOP” instruction， this two instructions should be followed “IE” instruction closely. 2. After CPU responding to an interrupt， IRQ should be cleared before resetting IE in order to avoid many responses to one interrupt. 3. Interrupt Enable instruction will be automatically cleared after entering interrupt-processing program. If setting IE too early， there is a possibility of re-entry the interrupt. So the Interrupt Enable instruction should be placed at the end and followed closely by two instructions include “RTNI”。 4. During the two successive instruction cycles next to Interrupt Enable instruction， CPU will not respond to any interrupts. 5. After CPU responding to interrupts， each bit of IE will be cleared by hardware while IRQ should be cleared by software.

　　Examples： Users should pay attention to some problems when writing program according to the above points. Here are some examples for the software application： Case One： Description： CPU will be activated when running to “HALT” or “STOP” instruction. Program： Interrupt Enable instruction is set outside the interrupt processing program …… LDI IE， 0FH ; enable interrupt NOP NOP HALT Analysis： After two “NOP” instructions， if an interrupt pulse comes or IRQ is non-zero during the third instruction cycle， CPU will respond to the interrupt and IE will be cleared. Then when returning to main program， CPU begins to execute “HALT” or “STOP” and will not be activated， because IE is cleared to zero and all interrupts are disabled now. Solution： “HALT” or “STOP” are put closely behind “LDI IE， 0FH” （According to point 1）